Great progress has been made over the past decade reducing power in integrated circuits while increasing the amount of signal processing. Historically power reduction has been achieved through voltage scaling, reduced capacitance, and innovative circuits and architectures. Shrinking feature sizes below 90 nm has resulted in proportional reductions in voltage and capacitance, while increasing static power consumption. The static power consumption in complementary metal oxide semiconductor (CMOS) process emanates from several leakage currents in transistors. The lower threshold voltages, thinner gate oxides, narrower field effect transistor (FET) channels, and high die temperatures drive sub threshold currents higher. The following conventional examples show the contribution of leakage power to total power for high performance conventional microprocessors:
For an Intel® 0.18 um technology, leakage power is approximately 10% of total power.
For an Intel® 0.13 um technology, leakage power is approximately 25% of total power.
For an Intel® 0.09 um technology, leakage power is approximately 50% of total power.
The leakage currents increase as a strong function of temperature. The major contributors to FET leakage current include P-N junction leakage, gate-induced drain leakage (GIDL), drain-induced barrier lowering (DIBL), punch through narrow width effect, weak inversion (sub threshold leakage), gate oxide tunneling, and hot carrier injection. For 65 nm and 45 nm technology nodes, sub threshold leakage is the dominant contributor and hence the primary candidate for design and process technology improvements. As technology nodes go below the 90 nm barrier, the leakage current dominates the power consumption of the integrated circuits (ICs), limiting the applications in mobile products where battery life is critical.
Conventional solutions for leakage control in digital logic design include multi-threshold CMOS (MTCMOS), which utilizes high-threshold voltage (Vt) transistors to disconnect low-Vt transistors from the power supply (e.g., Vdd) and/or ground (Gnd). One sleep transistor can be shared between many gates to create this virtual Vdd/Gnd connection. Alternatively, sleep transistors may be used at gate level. The granularity of the sleep transistor implementation can vary based on several factors. The main advantage of this approach is disconnecting the leakage path from both the supply and ground.
One disadvantage of the conventional solution includes utilization of dual-Vt devices, requiring additional process steps. Another disadvantage of the conventional solution is that one or two very large sleep transistors are used, which impacts both the performance and die area/cost penalty. A further disadvantage of the conventional solution includes reverse conduction through virtual ground and virtual power. Reverse conduction occurs where the drain of the transistor is more positive than the source. In addition, having two sleep transistors (e.g., a PMOS to shut off Vdd, and NMOS to disconnect from ground) degrades speed and reduces overhead voltage. In addition, the PMOS on-resistance (Ron) is usually 2 to 3 times larger than the NMOS on-resistance and, hence, either an asymmetrical rise time (tr) and fall time (tf) of the signal results. In order to compensate for this asymmetry with rise and fall times, a larger PMOS transistor is typically used, thus increasing the overall area of the circuit. Another disadvantage of the conventional solution is that of dependency of sleep transistor sizing to the data pattern loaded on the logic circuit. The data pattern of the logic circuit may include worst case parameters such as activity level or propagation delay of the circuit. As a result simulating the circuit under all possible input values may be an extremely difficult task, especially for large circuits.
There is no specific methodology for device size optimization that takes into account active mode power, propagation delay, turn-on time, turn-off time, activity factor, and sleep mode leakage. There is also no conventional technology to automate such digital logic design.